This invention is in the field of electronic integrated circuits for storing data states. Embodiments of this invention are more specifically directed to memory and latch circuits with immunity to single-event-upsets (SEUs).
Advances in manufacturing technology have enabled the design and construction of electronic integrated circuits with ever-increasing capability and functionality, at ever-decreasing cost. These important advances have done so, in large part, by reducing the feature sizes of active and passive semiconductor devices (e.g., transistors, resistors, capacitors, interconnections). As a result, higher density integrated circuits that operate at faster switching rates can now be manufactured, yet at lower cost because more integrated circuits can be manufactured simultaneously on a single semiconductor wafer.
The extreme miniaturization of semiconductor devices has involved certain vulnerabilities in the reliability of integrated circuit operation, however. One such vulnerability is referred to in the art as “single event upset”, or “SEU”. An SEU is a change of state in an integrated circuit caused by ionic or electromagnetic radiation impacting sensitive nodes in the circuit. This radiation is commonly caused by cosmic particles (“cosmic rays”) impacting atoms in close proximity to the integrated circuit, for example in the integrated circuit substrate, which releases free charge from ionization. An SEU occurs when this free charge is of a magnitude and polarity sufficient to change the state of a circuit node. An individual SEU typically has only a short-term effect on the operation of the circuit, as continued operation of the integrated circuit after the SEU will often cause the circuit to again reach a stable and correct operating state.
However, in integrated circuits deployed in inaccessible locations or providing critical “24/7” applications, an SEU can have longer-term effects with great consequences. For example, implantable medical devices such as cardiac pacemakers now have sophisticated computing circuitry, and remain in a powered-up state throughout their usable life. It is contemplated that, in some situations, an SEU causing a change in a stored data state in such a device could have long-lasting effect, requiring surgery to replace the upset device. In such applications, as well as in many other applications, it is desirable to design and construct the integrated circuits to be more tolerant of SEUs, so that stored data states or other steady-state conditions are not upset by SEUs of expected frequency and energy levels.
A typical conventional approach to improving the SEU stability of an integrated circuit is to intentionally provide collection capacitors at sensitive nodes in the integrated circuit. These collection capacitors, which may be separately constructed capacitors within the integrated circuit or simply intentionally increased parasitic capacitance at the sensitive circuit nodes, absorb the impinging free charge. This absorption allows the sensitive node to remain at its previous state or level, preventing the SEU. However, it has been observed, in connection with this invention, that the capacitance necessary to tolerate the amounts of charge that can cause an SEU is generally unknown, given the transient and variable nature of the causes of SEUs in practice. Especially as the miniaturization of transistors and passive devices continues, it has become impractical to use intentional capacitance to collect reasonable amounts of this transient charge.